Module ip_mac_rx_hash_g
Block Diagram of ip_mac_rx_hash_g
Overview
Name |
Direction |
Type |
Description |
|---|---|---|---|
pi_reset |
input |
wire logic |
Global Software/Hardware Reset (receive clock domain) |
pi_f_clock |
input |
wire logic |
Free Receive GMII/MII 125/25/2.5 MHz clock (from Clock Manager) |
pi_g_clock |
input |
wire logic |
Gated Receive GMII/MII 125/25/2.5 MHz clock (from Clock Manager) |
po_en_clock |
output |
var reg |
Receive GMII/MII 125/25/2.5 MHz clock gated clock enable |
pi_hash_addr |
input |
wire logic[8:0] |
From Receive EMAC Hash table index (9-MSB of CRC calculation over 48-bit destination address) |
pi_dest_addr |
input |
wire logic[47:0] |
Exact match (destination address of the frame) |
pi_new_match |
input |
wire logic |
Start a new search (match address, or hash filtering, toggle signal when new match should be prformed) |
pi_abort |
input |
wire logic |
Abort search (due to errors) |
pi_hash_nfix |
input |
wire logic |
Configuration Hash filtering + 1 Address match / 16 Address match |
pi_inverse |
input |
wire logic |
Inverse match |
pi_multicast |
input |
wire logic |
When asserted the imperfect filtering refers only for multicast addressees |
pi_pass_multi |
input |
wire logic |
Pass all multicast addresses |
pi_promisc |
input |
wire logic |
Promiscuos Mode (no DA filter) |
pi_pass_all |
input |
wire logic |
Pass all frames (bad or good) |
pi_rd_data |
input |
wire logic[47:0] |
Hash Table Memory access Memory (hash table) read data |
po_rd_addr |
output |
var reg[3:0] |
Memory (hash table) read address |
po_err_match |
output |
var reg |
Match Address Hit Address match output error |
po_match |
output |
var reg |
Address match output |
po_fc_match |
output |
var reg |
Address match output (control frame address) |
Always Blocks
- always @ ( posedge pi_f_clock or negedge pi_reset )
Gated Clock Enable
# |
Current State |
Next State |
Condition |
|---|---|---|---|
1 |
`IDLE |
`WAIT |
[(!(~ pi_reset) && !(pi_abort == 1’b0 && new_match == 1’b1 && pi_dest_addr == 48’h0180C2000001) && !(pi_abort == 1’b0 && new_match == 1’b1 && pi_promisc == 1’b1 || pi_pass_all == 1’b1) && !(pi_abort == 1’b0 && new_match == 1’b1 && pi_pass_multi == 1’b1 && pi_dest_addr[40] == 1’b1) && (pi_abort == 1’b0 && new_match == 1’b1 && pi_hash_nfix == 1’b1))] |
2 |
`IDLE |
`MATCH_1 |
[(!(~ pi_reset) && !(pi_abort == 1’b0 && new_match == 1’b1 && pi_dest_addr == 48’h0180C2000001) && !(pi_abort == 1’b0 && new_match == 1’b1 && pi_promisc == 1’b1 || pi_pass_all == 1’b1) && !(pi_abort == 1’b0 && new_match == 1’b1 && pi_pass_multi == 1’b1 && pi_dest_addr[40] == 1’b1) && !(pi_abort == 1’b0 && new_match == 1’b1 && pi_hash_nfix == 1’b1) && (pi_abort == 1’b0 && new_match == 1’b1))] |
3 |
`WAIT |
`IDLE |
[(!(~ pi_reset) && (pi_abort == 1’b1))] |
4 |
`WAIT |
`HASH |
[(!(~ pi_reset) && !(pi_abort == 1’b1))] |
5 |
`MATCH_1 |
`IDLE |
[(!(~ pi_reset) && (pi_abort == 1’b1)), (!(~ pi_reset) && !(pi_abort == 1’b1) && (pi_rd_data == pi_dest_addr)), (!(~ pi_reset) && !(pi_abort == 1’b1) && !(pi_rd_data == pi_dest_addr) && (po_rd_addr == 4’h0))] |
6 |
`HASH |
`IDLE |
[(!(~ pi_reset) && (pi_abort == 1’b1)), (!(~ pi_reset) && !(pi_abort == 1’b1) && (pi_rd_data[hash_idx] == 1’b1 && pi_dest_addr[40] == 1’b1 || pi_multicast == 1’b0))] |
7 |
`HASH |
`MATCH_2 |
[(!(~ pi_reset) && !(pi_abort == 1’b1) && !(pi_rd_data[hash_idx] == 1’b1 && pi_dest_addr[40] == 1’b1 || pi_multicast == 1’b0))] |
8 |
`MATCH_2 |
`IDLE |
[(!(~ pi_reset) && (pi_abort == 1’b1)), (!(~ pi_reset) && (po_rd_addr == 4’he) && !(pi_rd_data[47 : 32] == pi_dest_addr[47 : 32])), (!(~ pi_reset) && (po_rd_addr == 4’hf) && !(pi_rd_data[47 : 32] == pi_dest_addr[31 : 16])), (!(~ pi_reset) && (po_rd_addr == 4’h0) && (pi_rd_data[47 : 32] == pi_dest_addr[15 : 0])), (!(~ pi_reset) && (po_rd_addr == 4’h0) && !(pi_rd_data[47 : 32] == pi_dest_addr[15 : 0]))] |
Instances
- ip_emac_topip_emac_top
- mac_topip_mac_top_g
- mac_rx_topip_mac_rx_top_g
rx_hash
Imperfect filtering The EMAC Receive Hash/Exact Mach module is responsible for received frame filtering. For any incoming multicast frame, the EMAC applies the standard Ethernet cyclic redundancy check (CRC) function to the first 6 bytes that contain the destination address, then, if the hash filtering type is selected, the EMAC Receive Hash/Exact Mach module uses the most significant 9 bits (for a 512 bit hash table) of the result as a bit index into a table. If the indexed bit is set, the multicast frame is accepted. If the bit is cleared, the multicast frame is rejected. This filtering mode is called imperfect because frames not addressed to this station may slip through, but it still decreases the number of frames that the host can receive.
Perfect filtering The EMAC interprets a setup frame buffer in perfect filtering mode if the configuration bits are set accordingly. The EMAC can store 16 (programmable) destination addresses (full 48-bit Ethernet addresses). The EMAC compares the addresses of any incoming frame to these addresses, and also tests the status of the inverse filtering. It rejects addresses that: - Do not match if inverse filtering - Match if perfect filtering is set The setup frame must supply all 16 (programmable) addresses. Any mix of physical and multicast addresses can be used. Unused addresses should duplicate one of the valid addresses.