Module ip_mac_rx_state_g
Block Diagram of ip_mac_rx_state_g
Name |
Default value |
Description |
|---|---|---|
MEM_ADDR |
6 |
Name |
Direction |
Type |
Description |
|---|---|---|---|
pi_reset |
input |
wire logic |
Global Hardware/Software reset (active low) |
pi_f_clock |
input |
wire logic |
Free Receive GMII/MII 125/25/2.5 MHz clock (from Clock Manager) |
pi_g_clock |
input |
wire logic |
Gated Receive GMII/MII 125/25/2.5 MHz clock (from Clock Manager) |
po_en_clock |
output |
var reg |
Enable Receive GMII/MII 125/25/2.5 MHz clock (from Clock Manager) |
pi_gmii_val |
input |
wire logic |
gmii Data Valid, Data Input Signals and Alignment Error Receive MII/GMII data valid indication (from interface MII block) |
pi_gmii_data |
input |
wire logic[7:0] |
Receive MII/GMII error indication (from GMII block) |
pi_gmii_err |
input |
wire logic |
Receive MII/GMII data (MII data is pi_emac_rx_data[3:0]) (from interface MII block) |
pi_gigabit |
input |
wire logic |
Operating 1000 Mbps (Gigabit) mode |
pi_half_duplex |
input |
wire logic |
Operating Half Duplex mode |
pi_loopback |
input |
wire logic |
Loopback information (frame received in loopback mode) |
pi_little |
input |
wire logic |
Little endian data format (used for statistic word translation) |
po_fc_toggle |
output |
var reg |
Flow control Interface New pause frame received |
po_fc_value |
output |
var reg[15:0] |
Pause time (from FC frame decoding FSM) |
po_start |
output |
var reg |
Data Path Interface Start of data frame indication |
po_end |
output |
var reg |
End of data frame indication |
po_error |
output |
var reg |
Error indication (valid when end of frame or indicate statistic word) |
po_byte |
output |
var reg[1:0] |
Byte enable command, valid only when end of frame |
po_data |
output |
var reg[31:0] |
FIFO Data bus (frame data 32-bit word) |
pi_rd_addr |
input |
wire logic[MEM_ADDR:0] |
FIFO Control Interface Used by EMAC Receive State to see the momory state (full/empty/ready) |
po_wr_addr |
output |
var reg[MEM_ADDR:0] |
Write address (memory write address) |
po_wr_ptr |
output |
var reg[MEM_ADDR:0] |
Used by RX FIFO to compute the memory state (full/empty/ready) |
po_push |
output |
var reg |
Write enable command |
pi_err_match |
input |
wire logic |
Filterring Interface Address match error |
pi_match |
input |
wire logic |
Address match |
pi_fc_match |
input |
wire logic |
Address match (control frame address) |
pi_pass_all |
input |
wire logic |
Pass all frames (pass bad frames) |
po_hash_addr |
output |
var reg[8:0] |
Hash table index (9-MSB of CRC calculation over 48-bit destination address) |
po_dest_addr |
output |
var reg[47:0] |
Exact match (destination address of the frame) |
po_new_match |
output |
var reg |
Start a new search (match address, or hash filtering, toggle signal when new match should be prformed) |
po_abort |
output |
var reg |
Abort search (due to errors) |
pi_stop_rcv |
input |
wire logic |
Receive start/stop Receive MAC, receive stopped indication |
po_stop_rcv |
output |
var reg |
Receive MAC, receive stop command |
Always Blocks
- always @ ( posedge pi_f_clock or negedge pi_reset )
# |
Current State |
Next State |
Condition |
|---|---|---|---|
1 |
`WR_IDLE |
`WR_DATA |
[(!(~ pi_reset) && (po_stop_rcv == 1’b0 && gmii_valid == 1’b1 && gmii_eop == 1’b0))] |
2 |
`WR_DATA |
`WR_EXTEND |
[(!(~ pi_reset) && (gigabit_hd == 1’b1 && extend_ok == 1’b0 && gmii_eop == 1’b1))] |
3 |
`WR_DATA |
`WR_OVERRUN |
[(!(~ pi_reset) && !(gigabit_hd == 1’b1 && extend_ok == 1’b0 && gmii_eop == 1’b1) && (gmii_eop == 1’b1) && (full == 1’b1)), (!(~ pi_reset) && !(gigabit_hd == 1’b1 && extend_ok == 1’b0 && gmii_eop == 1’b1) && !(gmii_eop == 1’b1) && (counter[1 : 0] == 2’b00 && full == 1’b1))] |
4 |
`WR_DATA |
`WR_STAT |
[(!(~ pi_reset) && !(gigabit_hd == 1’b1 && extend_ok == 1’b0 && gmii_eop == 1’b1) && (gmii_eop == 1’b1) && !(full == 1’b1))] |
5 |
`WR_EXTEND |
`WR_OVERRUN |
[(!(~ pi_reset) && (extend_ok == 1’b1) && (full == 1’b1)), (!(~ pi_reset) && !(extend_ok == 1’b1) && (gmii_ext == 1’b0) && (full == 1’b1))] |
6 |
`WR_EXTEND |
`WR_STAT |
[(!(~ pi_reset) && (extend_ok == 1’b1) && !(full == 1’b1)), (!(~ pi_reset) && !(extend_ok == 1’b1) && (gmii_ext == 1’b0) && !(full == 1’b1))] |
7 |
`WR_OVERRUN |
`WR_STAT |
[(!(~ pi_reset) && (full == 1’b0 && gmii_valid == 1’b0 && int_val == 1’b0))] |
8 |
`WR_STAT |
`WR_IDLE |
[!(~ pi_reset)] |
Functions
- crc32_data8 ( logic[31:0] crc, logic[7:0] data )
CRC: 32 DATA: 8, POLY: 104C11DB7 next crc
Instances
- ip_emac_topip_emac_top
- mac_topip_mac_top_g
- mac_rx_topip_mac_rx_top_g
rx_state : ip_mac_rx_state_g#(.MEM_ADDR(10))
Receive memory address width (9 -> 512 locations, 10->1024)