Module ip_sync_reset_g

ip_sync_reset_g u_ip_sync_reset_g ( .pi_reset(pi_reset), .pi_clock(pi_clock), .pi_test_en(pi_test_en), .po_reset(po_reset) );

Block Diagram of ip_sync_reset_g

Overview

Synchronous resets are used in designs to safely reset the DFFs from one clock domain. The asynchronous reset can generate an unstable condition in design due to the metastability when reset is removed, if the DFF input data is different than the reset value output DFF data (for example a free counter)

Ports

Name	Direction	Type	Description
pi_reset	input	wire logic	Asynchronous reset
pi_clock	input	wire logic	Input clock
pi_test_en	input	wire logic	Test enable (multiplex information)
po_reset	output	wire logic	Synchronous reset (functional clock balanced)

Instances

• ip_emac_topip_emac_top

  • host_clk_mngip_host_clk_mng_g

    • host_sreset

    • hw_host_sreset

  • mac_topip_mac_top_g

    • mac_clk_mngip_mac_clk_mng_g

      • host_sreset

      • hw_host_sreset

      • mdio_sreset

      • rx_sreset

      • tx_sreset

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