Module ip_mac_cfg_hash_g
Block Diagram of ip_mac_cfg_hash_g
Overview
Name |
Direction |
Type |
Description |
|---|---|---|---|
pi_reset |
input |
wire logic |
Global Hardware Reset (host clock domain) |
pi_f_clock |
input |
wire logic |
Free HOST interface clock signal |
pi_g_clock |
input |
wire logic |
Gated HOST interface clock signal |
po_en_clock |
output |
var reg |
Enable HOST interface clock signal |
pi_wakeup |
input |
wire logic |
From/To Receive DMA Wake-up internal clock used by the Setup Frame FSM, |
pi_wr_data |
input |
wire logic[31:0] |
should be asserted at least 2 clock cycles (HOST clock) before asserting the pi_host_wr_setup (write enable) and can be de-asserted 2 clock cycles after Setup Frame complete Setup Frame data (HOST clock synchronous) |
pi_wr_setup |
input |
wire logic |
Setup Frame write enable (HOST clock synchronous) |
pi_hash_nfix |
input |
wire logic |
Configuration Hash filtering + 1 Address match / 16 Address match |
pi_little |
input |
wire logic |
Little endian |
po_wr_en |
output |
var reg[1:0] |
Hash Table Memory access Hash table write enable |
po_wr_data |
output |
var reg[47:0] |
Hash table write data |
po_wr_addr |
output |
var reg[3:0] |
Hash table write address |
Always Blocks
- always @ ( posedge pi_f_clock or negedge pi_reset )
Gated Clock Enable
# |
Current State |
Next State |
Condition |
|---|---|---|---|
1 |
`IDLE |
`WRITE_1 |
[(!(~ pi_reset) && (pi_wr_setup == 1’b1 && pi_hash_nfix == 1’b0)), (!(~ pi_reset) && !(pi_wr_setup == 1’b1 && pi_hash_nfix == 1’b0) && (pi_wr_setup == 1’b1 && pi_hash_nfix == 1’b1))] |
2 |
`WRITE_1 |
`IDLE |
[(!(~ pi_reset) && (pi_wr_setup == 1’b1 && pi_hash_nfix == 1’b0))] |
3 |
`WRITE_1 |
`WRITE_2 |
[(!(~ pi_reset) && !(pi_wr_setup == 1’b1 && pi_hash_nfix == 1’b0) && (pi_wr_setup == 1’b1 && pi_hash_nfix == 1’b1) && (po_wr_addr == 4’hf))] |
4 |
`WRITE_2 |
`WRITE_3 |
[(!(~ pi_reset) && (pi_wr_setup == 1’b1))] |
5 |
`WRITE_3 |
`WRITE_4 |
[(!(~ pi_reset) && (pi_wr_setup == 1’b1))] |
6 |
`WRITE_4 |
`IDLE |
[!(~ pi_reset)] |
Instances
- ip_emac_topip_emac_top
- mac_topip_mac_top_g
- mac_rx_topip_mac_rx_top_g
cfg_hash
A special configuration sequence must be performed before the reception process is started, except when it operates in promiscuous filtering mode. This is done by successively writing to CRFT configuration register. Depending on the selected filtering mode (CSR6[5:4] Filtering status field), the appropriate information should be written into the CRFT (see EMAC Functional Specification 1.1)
When hash multicast or hash filtering operating mode is selected, 16 consecutive writes should be performed to the CRFT register, representing the 512-bit hash table information. After completing the hash table write, two additional writes should be performed on CRFT encapsulating the perfect 48-bit MAC address used for exact physical destination address match processing.
When perfect filtering mode is selected 32 consecutive writes should be performed to the CRFT register encapsulating 16 exact match addresses.
The structure of each 32 bit word written to CRFT register depends on CSR0[7] (Big/Little Endian field) and CSR6[5:4] (Filtering status field). See 9.2.1 and 9.2.2 for a detailed description of CRFT configuration sequence.