Module ip_mac_fc_dec_g
Name |
Direction |
Type |
Description |
---|---|---|---|
pi_reset |
input |
wire logic |
|
pi_f_clock |
input |
wire logic |
Free Receive GMII/MII 125/25/2.5 MHz clock (from Clock Manager) |
pi_g_clock |
input |
wire logic |
Gated Receive GMII/MII 125/25/2.5 MHz clock (from Clock Manager) |
po_en_clock |
output |
var reg |
Enable Receive GMII/MII 125/25/2.5 MHz clock (from Clock Manager) |
pi_gigabit |
input |
wire logic |
Operating 1000 Mbps (Gigabit) mode |
pi_xmit_nfc |
input |
wire logic |
Transmit FSM data frame transmit enable (when full duplex) |
pi_fc_enable |
input |
wire logic |
NOTE: This signal is not asserted during flow control frame transmission Receive flow control enable (flow control decoding enable) |
pi_fc_toggle |
input |
wire logic |
New pause frame received (pi_fc_value valid) |
pi_fc_value |
input |
wire logic[15:0] |
Pause time (from RX EMAC, FC frame decoding) |
po_fc_tx_off |
output |
var reg |
Received FC packet (Transmit stop command) |
Instances
- ip_emac_topip_emac_top
- mac_topip_mac_top_g
- mac_rx_topip_mac_rx_top_g
fc_dec
Global Software/Hardware Reset (receive clock domain)