DVT SystemVerilog IDE User Guide
Rev. 21.1.18, 28 April 2021
To add a new port to a module, place the editor cursor on the module name, right-click and select Refactor > Add port.
In the Add port wizard you can tune the name, direction, type, and width of the new port.
Click Ok to perform the refactoring or Preview to see the changes that are about to be performed in the source code.
Note: An empty port connection is added to all the instances of the selected module along with a FIXME comment which shows up in the Tasks View. See Track Tasks using TODO Markers
Tip: In the Preview page you can select what changes should be performed.