DVT SystemVerilog IDE User Guide
Rev. 23.1.7, 15 March 2023

27.10.2 Bit Field Diagrams for packed data types

DVT can render bit field diagrams from packed data types declarations in tooltips and in the Inspect View.

Trigger the tooltip from the Editor, by hovering a packed struct or union data type:

Declaration Tooltip Window Notes
The memory layout is represented horizontally from MSB to LSB.
Nested types are represented vertically.
Union members are separated with a blank line.
Additional information, for example the type of a member, can be found in the table below the diagram.

To see the diagram in the Inspect View, simply click on a packed struct or union data type in the Editor:

Tip: To save the diagram as an SVG file, right-click on it in the Inspect View.

Tip: Inspect View offers zoom and pan functionality for diagrams which exceed 64 bits.

Note: Diagrams are rendered using the BitField library.