DVT SystemVerilog IDE User Guide
Rev. 24.1.3, 13 February 2024

27.5 UVM Components Diagrams

UVM Components Diagrams help you inspect and document the structure of a verification environment.

You can create a component diagram in one of the following ways:

  • Right-click in the Verification Hierarchy View and select Show Diagram. This way is faster, but the generated diagram might not be completely accurate because it's missing the runtime information.

  • Generate the diagram using the simulator and open it in DVT. This way requires to run the simulation with some additional files compiled, but the generated diagram will be complete.

The following operations are available in the right-click context menu:

  • Go to Create Call Jump to the create call for the selected instance.

  • Go to Type Jump to the declaration of the selected element's type. It is available for nodes and labeled edges.