DVT SystemVerilog IDE User Guide
Rev. 21.1.18, 28 April 2021
A fragment of a module can be automatically extracted and encapsulated into a new instance.
The fragment must be a contiguous region containing only instances, always blocks and assignments.
Select the region in the editor, press Ctrl+1, select Extract to module from the list of quick assist proposals and press Enter.
The selected piece of code will be moved to a new module in a new file. Fill in the name of the new module and file.
The initial selection is replaced with an instance of the new module:
The ports of the new module are automatically computed and connected in the instantiation.
Tip: You can also right-click in the editor and go to Refactor > Extract to module to trigger this functionality.