DVT SystemVerilog IDE User Guide
Rev. 23.2.28, 28 November 2023

41.2.3 Unelaborated Design

The unelaborated design is the part of the compiled code not under any of the elaboration tops. It can divided into two categories:

  1. Inactive generate constructs: e.g. the else branch of an if generate, all inactive case items, for loop generates with no iterations

  2. Design elements not instantiated under the elaboration tops: unused interfaces, the design of an instance under an inactive generate construct

Tool functionality in the unelaborated part of the design can be restricted through the +dvt_unelaborated_compile_checks build config directive. A faster build time is the main benefit. But, the tradeoff is the loss of all IDE specific functionality, like for example Show Usages, Rename Refactoring, or Design Diagrams, in the excluded code.