DVT SystemVerilog IDE User Guide
Rev. 23.1.8, 29 March 2023
Table of Contents
DVT analyzes power format files (either UPF or CPF) and presents power domain information in:
Power format project nature
In order to work with power format files, you have to enable the Power Format nature for your project.
The Power Format nature works only in conjunction with at least one of Verilog or VHDL natures.
Power format files
Use one of the following build configuration directives to specify a power format file to be analyzed:
Power format analysis
At full build, after elaborating the design, DVT analyzes (interprets) the provided power format file and elaborates the power domains. TCL and power domain errors are detected and reported during this phase.
All analyzed power format files are decorated with a blue bullet. Files outside the project directory are automatically linked under the DVT Auto-Linked folder.
Implementation Note: By default, the working directory of the TCL interpreter is the DVT project directory. To change it, use +dvt_compilation_root within the invocation where the power format file is specified, for example:
Implementation Note: Environment variables defined using +dvt_setenv within the invocation where the power format file is specified are available in the TCL $::env array.
Tip: To print power format analysis debug information in the DVT Build Console add this directive to your build configuration file:
Tip: If a file called dvt_pre_interpret.tcl exists in any of the the User and Common Settings Locations it will be interpreted before the provided power format file. If several such files exist, they will all be interpreted, in precedence order of the User and Common Settings Locations. This mechanism allows you to define TCL variables or functions for debugging or deployment purposes.
Incremental power format analysis
Whenever you change a power format file which was analyzed during the full build phase, DVT triggers a power format file analysis and a power domain elaboration.
Whenever you change a design file (Verilog or VHDL) which was compiled during the full build phase, DVT triggers a power domain elaboration (analysis of power format files is not performed).
The following Common Power Format (CPF) and Unified Power Format (UPF) commands are supported by DVT:
create_power_domain -name <power_domain_name> -default -instances <instance_list> -exclude_instances <instance_list>
create_power_domain <power_domain_name> -elements <instance_list> -exclude_elements <instance_list> -include_scope -scope <scope>