DVT SystemVerilog IDE User Guide
Rev. 23.1.22, 22 September 2023

13.3 Vertical Alignment

When enabled, this option performs vertical alignment.

  • Vertical Alignment Tokens

The lines of code inside the same scope are aligned by the specified comma separated list of vertical alignment tokens. Vertical alignment is performed left to right, by the same token. For example assuming '=' and ':' as vertical align tokens: In order to use the comma character ',' as a vertical alignment token, the character must be preceded by the escaping character '\'.

Before After (":" token)
  • Only consecutive lines - When enabled, only consecutive lines are vertically aligned. Two lines are consecutive if they follow each other or are separated by comment lines.

Before After
  • Vertical align single line comments - When enabled, single line comments are aligned.

Before After
  • Vertical align to open parenthesis - When enabled, vertical align to open parenthesis.

Before After
  • Vertical align to open curly - When enabled, vertical align to open curly.

Before After
  • Independent `ifdefs - When enabled, `ifdefs are independent alignment scopes:

Before After
  • Vertical Align Patterns - By Name Port Connections - When enabled, this pattern aligns instance port connections by name:

Before After
  • Vertical Align Patterns - Class Declarations - When enabled, this pattern aligns class parameters:

Before After
  • Vertical Align Patterns - Class Variable Declarations - When enabled, this pattern aligns class variables:

Before After
  • Vertical Align Patterns - `defines - When enabled, this pattern aligns `defines:

Before After
  • Vertical Align Patterns - Function Declarations - When enabled, this pattern aligns function and task declarations:

Before After
  • Vertical Align Patterns - Function Variable Declarations - When enabled, this pattern aligns function and task

Before After
  • Vertical Align Patterns - Interface Port Declarations - When enabled, this pattern aligns interface ports:

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  • Vertical Align Patterns - Interface Signal Declarations - When enabled, this pattern aligns interface signals:

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  • Vertical Align Patterns - Module Port Declarations - When enabled, this pattern aligns module ports:

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  • Vertical Align Patterns - Module Signal Declarations - When enabled, this pattern aligns module signals:

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  • Vertical Align Patterns - `xvm_field macros - When enabled, this pattern aligns `xvm_field factory registration macros:

Before After