DVT SystemVerilog IDE User Guide
Rev. 21.1.8, 1 March 2021
You can easily rename a variable, signal, method, etc. within the current file.
Place the editor cursor on its name, press Ctrl+1, select Rename ... in file from the list of quick assist proposals and press Enter.
Type in the new name and press Enter again when done.
Tip: This is a lightweight Rename Refactoring which you should use in contexts where the renamed element is local to the file: local parameters, method argument names, local variables, signals of a module, etc.
Tip: You can also right-click in the editor and go to Refactor > Rename in File.