DVT SystemVerilog IDE User Guide
Rev. 21.1.13, 5 April 2021
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Chapter 25. Code Factory

The Code factory allows you to easily generate instances, signals and testbenches starting with modules or entities.

Factory Input

It is required that you first set an input. Right-click on the element definition and select from the context menu the option Set Factory Input under Code Factory.

The current input persists until a new one is set or until a full build is invoked.

Creating code

Having set an input, you can do one of the following:

  • Create Instance for instantiating the design element;

  • Create Signals for listing the ports of the design element as signals;

  • Create Testbench for defining a testbench that instantiates the design element with all the required port connections already made;

The code will be inserted at the cursor's current position.

Any information or errors during Code Factory operations are shown in the status bar.

Notes

  • At the moment you can set only SystemVerilog modules and VHDL entities as factory input.

  • Cross language operations are not supported. You can't set a SystemVerilog module as input and use it in VHDL for creating output and vice-versa.

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