DVT SystemVerilog IDE User Guide
Rev. 23.1.21, 12 September 2023
You can easily expand .* wildcard named port connections to explicit named port connections.
Place the editor cursor either on a module or interface instance declaration and press Ctrl+1, select Expand .* port connections from the list of quick assist proposals and press Enter.
The .* connections are expanded to named port connections.
Note You can customize the look and feel of the explicit named port connections from Window > Preferences > DVT > SystemVerilog > Editor > Content Assist.
Tip: You can also right-click in the editor and go to Refactor > Expand .* Port Connections.