DVT SystemVerilog IDE User Guide
Rev. 21.1.31, 27 July 2021
Renaming a file will automatically update its references across the project, such as include directives.
There are multiple ways to perform this operation.
You will be prompted to choose a new name for the selected file.
Click OK to perform the refactoring operation, or Preview to see the changes that are about to be performed in the source code. In the Preview page you can select which changes will be performed, and then click Finish.
(1) You can select a file/change to see the source differences produced by the refactoring.
(2) Uncheck a file/change to prevent those changes from being applied.
Tip: Matches hidden inside a macro call cannot be automatically renamed. Instead, DVT will insert a FIXME comment above the macro call to indicate that it should be refactored by hand.
(1) These matches are marked with the tag Inside Macro.
(2) You can apply a filter to list only this type of matches.