DVT SystemVerilog IDE User Guide
Rev. 21.1.8, 1 March 2021
To generate the Component Diagrams from simulation, some additional arguments must be added to the build directives, depending on the simulator.
When the simulation starts, a component_hierarchy_of_<test_name>.chd will be generated in the working directory. Open the generated file in DVT to inspect the diagram.
The location of the diagram can be changed by setting the DVT_CHS_FILE environment variable before running the simulation.
export DVT_CHS_FILE=/path/to/a/components_diagram.chd # sh, bash
You can stop the test immediately after the diagram has been generated by setting the DVT_CHS_STOP_TEST environment variable before running the simulation.
export DVT_CHS_STOP_TEST=true # sh, bash