DVT SystemVerilog IDE User Guide
Rev. 21.1.8, 1 March 2021
An Override Annotation indicates that a function/task overrides a parent class implementation.
Override annotations are triangles on the vertical ruler to the left of the editor, next to the function definition:
Hover an override annotation to see the overridden parent.
Click on an override annotation to jump to the parent function that is overridden.