DVT SystemVerilog IDE User Guide
Rev. 23.2.28, 28 November 2023
The Verification Hierarchy View presents the UVM object instance tree. An UVM object instance is a class member of an UVM based type that is created using an UVM factory create call.
To populate the view, go to the UVM menu and Select Verification Top or use the view toolbar button.
For the selected UVM test, you have the option to view a statically elaborated hierarchy or perform a runtime elaboration in order to view testbench structures accurately reflecting the configuration at start of simulation.
The view label shows the current project, the current top component and the number of instances in the hierarchy.
You can double-click on any component to go to its UVM factory create call.
Right-click on an instance in the hierarchy and you have the following options :
You can double-click on any port to go to its declaration.
Right-click on a port and you have the options to search for its usages, its layers and for its type hierarchy, also you can copy its name and the full hierarchy path of the selected port.
You can use the filters to locate a specific instance or port. You may use slash '/' characters to filter hierarchically one level and '//' to filter hierarchically all the levels. You may use the dot '.' character to filter instances that contain a specific port. See Quick Search for more details.
For example, filtering hierarchically all the levels for a specific port name :