DVT SystemVerilog IDE User Guide
Rev. 18.1.33, 18 October 2018
Show Diagram on a state variable inside a module or entity will generate a Finite-State Machine (FSM) diagram. States and transitions are automatically detected in the enclosing scope by analyzing all the assignments and conditions in which the state variable is used.
Multiple transitions between the same two states are merged into a single one with multiple conditions.
Next state variables are supported. Method call transitions and "one-hot" array case conditions are not supported.
The initial state is colored gray.
Selecting any state or transition will highlight the previous and next states differently.
You can change the look and feel of the diagram using the preferences from the Diagram Toolbar.