DVT SystemVerilog IDE User Guide
Rev. 21.1.18, 28 April 2021
Some simulators define proprietary pre-processing that might have some implications on the actual simulated code (see for example in OVM lib ifdef INCA occurrences).
Also, many times, compilation/run scripts take as arguments macro definitions.
See Build Configurations for enhanced support of simulator commands files.
Until we'll fully integrate with all simulators and/or we provide preferences for specifying macros and means for easily turning them on/off, we recommend to create a dummy *.sv file that you set first in the top files project property as follows:
Dummy macros might look like: