DVT SystemVerilog IDE User Guide
Rev. 21.1.44, 19 October 2021

26.16.3 Structural Changes Preview Diagram

Any change to a module or entity definition, like new ports or new signals being added, affects all its instances. Before proceeding to source code changes, you can preview the design structural changes.

Terminology:

  • output instance is the module instance where the connection starts. It outputs the signal that will be connected. output module is the module being instantiated as an output instance.

  • input instance is the module instance where the connection ends. It inputs the signal that will be connected. input module is the module being instantiated as an input instance.

  • closest parent instance is the parent instance through which a signal is routed to connect the ports leading from the output instance to the input instance across the design hierarchy. No ports will be added to the closest parent instance. The closest parent module is the module corresponding to the closest parent instance.

  • relevant modules are the modules that will change by adding new ports and/or new signals. relevant instances are instances of relevant modules.

Ports are added only to modules that are instantiated on the paths leading from the output module instance and the input module instance to the closest parent instance. Ports are added to the output module or the input module only if the connection is not using an existing port.

All relevant instances are colored in green in the preview diagram. All the instances that will not change are colored in blue.

They are hidden by default but the Show Side Effects button from the left side of the diagram can be used for showing them.