DVT SystemVerilog IDE User Guide
Rev. 21.1.44, 19 October 2021
Any change to a module or entity definition, like new ports or new signals being added, affects all its instances. Before proceeding to source code changes, you can preview the design structural changes.
Ports are added only to modules that are instantiated on the paths leading from the output module instance and the input module instance to the closest parent instance. Ports are added to the output module or the input module only if the connection is not using an existing port.
All relevant instances are colored in green in the preview diagram. All the instances that will not change are colored in blue.
They are hidden by default but the Show Side Effects button from the left side of the diagram can be used for showing them.