DVT SystemVerilog IDE User Guide
Rev. 21.1.14, 13 April 2021
When you want to uniformly name a port which is directly propagated across several levels of the design, you can use Rename across the Design Hierarchy refactoring.
If the port is directly connected to a sub instance port, then the sub instance port will also be renamed, and so on recursively across the whole sub design hierarchy tree.
If the port is directly connected to a parent instance port, then the parent instance port will also be renamed only if it is part of the current editor instance breadcrumb path, and so on recursively up the design top.
For every port, both the definition and all its references are renamed.
Place the editor cursor on the port, right click and select Refactor > Rename Port Across the Design Hierarchy.
A dialog pops-up and allows you to configure:
Note That the full hierarchical path to the refactoring starting port is highlighted in yellow.
You can Preview the changes in a Schematic diagram.
The diagram shows all the instances, ports and port connections affected by the refactoring.
Note: Naming conflicts can appear when:
When done previewing, click the Resume button on the Diagram Editor top bar to return to the refactoring dialog.
You can also preview the changes using a source code diff by clicking the Preview > button.
Click OK to perform the refactoring.