DVT SystemVerilog IDE User Guide
Rev. 21.1.44, 19 October 2021
Start by inspecting the module hierarchy in the Design Hierarchy View. All traces are going to be computed on this design hierarchy.
You can trace across the whole design (when you pick a top module as the hierarchy root) or focus on a specific module in the design (when you pick that module as the hierarchy root). The Design Hierarchy View documentation provides more details on how to populate this view.
Select an instance and click on the Show/Hide Ports button in the toolbar.
Then right click on a port and select one of the trace kinds, for example Trace Drive and Load.
The Trace Connections View opens.
Note 1 Signals are traced across port connections and combinational logic: continuous assignments and combinational always blocks in SystemVerilog, concurrent signal assignments and combinational processes in VHDL.
Note 2 Interface and struct type signals are supported.