DVT SystemVerilog IDE User Guide
Rev. 21.1.13, 5 April 2021
You can trace connections directly from the DVT editor.
All trace kinds ( Trace Drive, Trace Load, Trace Drive and Load) are available.
Start by placing the editor cursor over a port or internal signal and select Trace > trace kind from the right-click context menu.
IMPLEMENTATION NOTE: Tracing Connections from Editor works within the current design hierarchy, found in the Design Hierarchy View. The Design Hierarchy View documentation provides more details on how to populate this view.
The Trace Connections View opens.
Note 1 Signals are traced across port connections and combinational logic: continuous assignments and combinational always blocks in SystemVerilog, concurrent signal assignments and combinational processes in VHDL.
Note 2 Interface and struct type signals are supported.
Note 3 The current breadcrumb navigation bar is used to determine the module instance to which the traced signal belongs. See Breadcrumb Navigation Bar for more details.