DVT SystemVerilog IDE User Guide
Rev. 19.1.34, 11 October 2019

40.10.17 UVM Browser View

The UVM Browser View is an intuitive entry point for exploring all the classes of a UVM-based verification environment.

It allows you to explore UVM-based classes grouped by categories, like agents, monitors, drivers or sequences and easily inspect the UVM flow specific API, like overridden phases, class members registered to the factory or TLM ports.

Open the view from menu Window > Show View > Other... > DVT > UVM Browser.

You can use CamelCase or Simple Regex to locate a specific element.

Toolbar   
Prepend Package Name Prepend the enclosing package name to the name of each class, useful when you explore for example all agents across packages.
Group By Package Group classes by package. You may chose to see for example all agents across packages or to explore all categories in a specific package.

The top UVM Types Panel presents all the UVM-based classes defined in your verification environment. For convenience they are grouped by categories like agents or monitors.

The inheritance hierarchy between classes is shown up to the UVM base class.

Description
Class is declared under a different package than the parent package presented in the view's tree because one of its children are declared under that parent package and "Group by Package" is enabled.
Physical sequencer or sequence. A physical sequencer is a sequencer that is connected to a driver. A physical sequence always extends uvm_sequence parameterized with a class that extends uvm_sequence_item and contains `uvm_declare_p_sequencer macro with a physical sequencer as argument.

The categories and their corresponding base classes are the following

Categories Base class Notes
Agentsuvm_agent 
Driversuvm_driver 
Envsuvm_env 
Itemsuvm_sequence_item 
Monitorsuvm_monitor 
Memoriesuvm_mem 
Other Componentsuvm_componentAny class deriving from uvm_component which does not fall into any other category within this table.
Other Objectsuvm_object 
Portsuvm_port_base, uvm_tlm_if_base,


uvm_tlm_extension_base, uvm_sqr_if_base,


uvm_tlm_req_rsp_channel, uvm_tlm_fifo_base
 
Registersuvm_reg 
Backdoor Registersuvm_reg_backdoor 
Frontdoor Registersuvm_reg_frontdoor 
Register Adaptersuvm_reg_adapter 
Register Blocksuvm_reg_block 
Register Fieldsuvm_reg_field 
Register Sequencesuvm_reg_sequence 
FIFO Registersuvm_reg_fifo 
Register Filesuvm_reg_file 
Register Mapsuvm_reg_map 
Register Predictorsuvm_reg_predictor 
Scoreboardsuvm_scoreboard 
Sequencersuvm_sequencer 
Sequencesuvm_sequence 
Testsuvm_test 

The bottom Members Panel panel displays class members. You can toggle the UVM Members Mode on/off using the button.

In UVM Members Mode it displays the following members:

  • Virtual interfaces

  • Class members registered to the factory using the `uvm_field... macros

  • Class members of an UVM-based type (TLM ports included)

  • Overridden functions and tasks from parent UVM base classes

When the UVM Members Mode is off, the Members Panel behaves exactly like the Members Panel of the Type Hierarchy View.