DVT SystemVerilog IDE User Guide
Rev. 18.1.33, 18 October 2018

29.1 Simulation Prerequisites

Simulator switches for SystemVerilog and VHDL

In order for DVT to communicate with the simulator, you need to pass the simulator a set of switches. The table below details the required switches per simulator:

Xceliumxrun -linedebug -input "@source $DVT_HOME/libs/dvt_debug_tcl/dvt_debug.tcl" ...
IUSirun -linedebug -input "@source $DVT_HOME/libs/dvt_debug_tcl/dvt_debug.tcl" ...
VCSvcs -debug_all ...


./simv -ucli -i "$DVT_HOME/libs/dvt_debug_tcl/dvt_debug.tcl" ...
Questasimvlog -O0 -novopt ...


vsim -novopt -do "do $DVT_HOME/libs/dvt_debug_tcl/dvt_debug.tcl" ...


Note: When running vsim with -qwavedb option, the Variables View may not be populated correctly (missing local and class variables).

NOTE: In general, simulation runs slower when debugging is enabled. This has nothing to do with the DVT-Simulator integration. The extent of this effect is simulator-specific.

NOTE: The -qwavedb flag of vsim is known to interfere with the proper display of local and class variable in the Variables View.

The dvt_sn_debug Library for e-Language

In order for DVT to communicate with Specman, you need to load or precompile the dvt_sn_debug library into Specman.

The library is typically located in the $DVT_HOME/libs folder, which you should add to your $SPECMAN_PATH

For example:

irun $DVT_HOME/libs/dvt_sn_debug/e/dvt_top.e ....

The dvt_sn_debug library implements the communication between DVT and Specman in debug mode. It doesn't add any simulation overload.

Communication between DVT and the simulator is done:

  • when you connect

  • when a breakpoint is hit

  • when you switch threads or frames

  • when you inspect variables (they are fetched lazily)

  • when you add/remove or enable/disable breakpoints while being connected to the simulator