DVT SystemVerilog IDE User Guide
Rev. 19.1.20, 7 June 2019

39.5.1 Icons

Regular Verilog/SystemVerilog File
Linked Resource Verilog/SystemVerilog File


See Linked Resources.
Out of Project Verilog/SystemVerilog File


The file is not inside a project directory, nor accessible as a linked resource. Functionality is limited on "gray" files.
Library
Package
Program
Typedef
Class
Interface
Module
Checker
Primitive
Generate
Field
Enumeration name
Constructor
Function
Task
Event
Fork/join - Indicates a fork block.
Process - Indicates a process in a fork block.
Constraint
Cover Group
Input Port
Output Port
Bidirectional Port
Interface Port
ModPort
Port passed multiple times when tracing a signal
Wire
Port connection
Always
Assign
Module Instance
Unknown Instance
Interface Instance
Object Instance - Relevant for XVM methodologies, indicates a "created" object.
Component Instance - Relevant for XVM methodologies, indicates a "created" component.
Test Class - Relevant for XVM methodologies, indicates a "test" class.
Sequence - Relevant for XVM methodologies, indicates a "sequence" class.
Sequence Item - Relevant for XVM methodologies, indicates a "sequence item" class.
Root Class - Relevant for XVM methodologies, indicates the "root" class.
Preprocessing define
Preprocessing undefine
Preprocessing ifdef, ifndef
Code Template For example in autocomplete proposals.