DVT SystemVerilog IDE User Guide
Rev. 21.1.24, 8 June 2021

26.16.1 Connect Instances Using New Ports

In order to connect two module instances using new ports, you must specify the output instance (the signal source) and the input instance (the signal destination). New ports will be created across the design hierarchy as needed, in order to propagate the signal.

IMPORTANT NOTE: This feature is currently supported only in the Old Design Hierarchy View. To switch to/from the Old Design Hierarchy View, go to Window > Preferences > DVT and toggle Switch to Old Design Hierarchy View

  1. Press the Select Top button and pick one of the available design tops.

  2. Press the Show Connect Toolbar button to bring up the Connect Instances Toolbar .

  3. Right click on an instance and select Connect Output from the context menu.

    The output instance is presented in the connect toolbar Output textbox:

  4. Select another instance, right click and Connect Input.

    The input instance is presented in the connect toolbar Input textbox along the previous set output instance:

  5. You can Preview Structural Changes in the Design Hierarchy .

  6. Press the Connect button. The Refactor Connect dialog pops-up. Here you can tune the port and signal names, as well as other refactoring parameters.

  7. Press the Preview button to preview the source code changes:

  8. Press the OK button in order to perform the changes.

Note 1: At any time you can change the connection output or input. Pick the direction using the radio buttons, select another instance, then right click Connect Input/Output.

Note 2: You can undo the whole refactoring operation using Undo ( Ctrl+Z).