DVT SystemVerilog IDE User Guide
Rev. 21.1.40, 21 September 2021

5.3 Synthesis Checks

ID Message
SIGNAL_MULTIPLE_DRIVERSSignal # has multiple drivers
SENSITIVITY_MISSINGMissing # from sensitivity list
SENSITIVITY_MIXED_CONTROLMixed edge/non-edge controls in sensitivity list may not be synthesizable
ASSIGNMENT_BLOCKINGBlocking assignment of # in sequential logic (use non-blocking assignment)
WIDTH_MISMATCH_PADDINGAssignment to #-bit value from #-bit value
WIDTH_MISMATCH_ROUNDINGAssignment to #-bit value from #-bit value
WIDTH_MISMATCH_TRUNCATIONAssignment to #-bit value from #-bit value
WIDTH_MISMATCH_IMPLICIT_SIGNALImplicit signal(s) # of type # is/are connected to port # of type #
WIDTH_MISMATCH_IMPLICIT_SIGNALImplicit signal(s) # of type # is/are assigned to signal # of type #
UNDRIVEN_INPUT_PORTInput port # is not driven
PORT_CONNECTIONInput port # connected to an output port
PORT_CONNECTIONOutput port # connected to an input port
PORT_CONNECTIONCannot drive input port #
PORT_CONNECTIONOutput port # of sub-instance # connected to a reg data type signal
SIGNAL_NOT_RESETSignal # is not reset
MULTIPLE_CLOCKS_BLOCKProcedural block driven by multiple clocks (#)
MULTIPLE_RESETS_BLOCKProcedural block driven by multiple resets (#)
MULTI_BIT_EDGE_CONTROLMulti-bit signal # used as edge control
OUTPUT_PORT_READReading from an output port # is not recommended
FEEDTHROUGH_DETECTEDFeedthrough from # to #
INTERNAL_GENERATED_CLOCKClock signal # is not an input port
INTERNAL_GENERATED_RESETReset signal # is not an input port
IMPLICIT_DECLARATIONImplicit declaration of # using `default_nettype set to #