Class uvm_mem_shared_access_seq

• uvm_pkg :: uvm_void

  • uvm_pkg :: uvm_object

    • uvm_pkg :: uvm_transaction

      • uvm_pkg :: uvm_sequence_item

        • uvm_pkg :: uvm_sequence_base

          • uvm_pkg :: uvm_sequence

            • uvm_pkg :: uvm_reg_sequence

              • uvm_pkg :: uvm_mem_shared_access_seq

Reset

Inheritance Diagram of uvm_mem_shared_access_seq

Verify the accessibility of a shared memory by writing through each address map then reading it via every other address maps in which the memory is readable and the backdoor, making sure that the resulting value matches the written value.

If bit-type resource named "NO_REG_TESTS", "NO_MEM_TESTS", "NO_REG_SHARED_ACCESS_TEST" or "NO_MEM_SHARED_ACCESS_TEST" in the "REG::" namespace matches the full name of the memory, the memory is not tested.

uvm_resource_db#(bit)::set({"REG::",regmodel.blk.mem0.get_full_name()},
                           "NO_MEM_TESTS", 1, this);

The DUT should be idle and not modify the memory during this test.

Variables

Name	Type	Description
mem	uvm_mem	The memory to be tested

Constructors

function new ( string name )

Tasks

virtual function body ( )

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