Class uvm_reset_phase

• uvm_pkg :: uvm_void

  • uvm_pkg :: uvm_object

    • uvm_pkg :: uvm_phase

      • uvm_pkg :: uvm_task_phase

        • uvm_pkg :: uvm_reset_phase

Reset

Inheritance Diagram of uvm_reset_phase

Reset is asserted.

uvm_task_phase that calls the uvm_component::reset_phase method.

Upon Entry

• Indicates that the hardware reset signal is ready to be asserted.

Typical Uses

• Assert reset signals.

• Components connected to virtual interfaces should drive their output to their specified reset or idle value.

• Components and environments should initialize their state variables.

• Clock generators start generating active edges.

• De-assert the reset signal(s) just before exit.

• Wait for the reset signal(s) to be de-asserted.

Exit Criteria

• Reset signal has just been de-asserted.

• Main or base clock is working and stable.

• At least one active clock edge has occurred.

• Output signals and state variables have been initialized.

Variables

Name	Type	Description
type_name	string

Functions

static function uvm_reset_phase get ( )

Returns the singleton phase handle

virtual function string get_type_name ( )

Tasks

virtual function exec_task ( uvm_component comp, uvm_phase phase )

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