Class uvm_run_phase
- uvm_pkg :: uvm_void
Inheritance Diagram of uvm_run_phase
Name |
Type |
Description |
|---|---|---|
type_name |
string |
Functions
- static function uvm_run_phase get ( ) [source]
Returns the singleton phase handle
Tasks
- virtual function exec_task ( uvm_component comp, uvm_phase phase ) [source]
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Stimulate the DUT.
This uvm_task_phase calls the uvm_component::run_phase virtual method. This phase runs in parallel to the runtime phases, uvm_pre_reset_phase through uvm_post_shutdown_phase. All components in the testbench are synchronized with respect to the run phase regardless of the phase domain they belong to.
Upon Entry
Indicates that power has been applied.
There should not have been any active clock edges before entry into this phase (e.g. x->1 transitions via initial blocks).
Current simulation time is still equal to 0 but some "delta cycles" may have occurred.
Typical Uses
Components implement behavior that is exhibited for the entire run-time, across the various run-time phases.
Backward compatibility with OVM.
Exit Criteria
The DUT no longer needs to be simulated, and
The uvm_post_shutdown_phase is ready to end
The run phase terminates in one of two ways.
When all objections on the run_phase objection have been dropped, the phase ends and all of its threads are killed. If no component raises a run_phase objection immediately upon entering the phase, the phase ends immediately.
The phase ends if the timeout expires before all objections are dropped. By default, the timeout is set to 9200 seconds. You may override this via uvm_root::set_timeout.
If a timeout occurs in your simulation, or if simulation never ends despite completion of your test stimulus, then it usually indicates that a component continues to object to the end of a phase.