Class uvm_pre_reset_phase

• uvm_pkg :: uvm_void

  • uvm_pkg :: uvm_object

    • uvm_pkg :: uvm_phase

      • uvm_pkg :: uvm_task_phase

        • uvm_pkg :: uvm_pre_reset_phase

Reset

Inheritance Diagram of uvm_pre_reset_phase

Before reset is asserted.

uvm_task_phase that calls the uvm_component::pre_reset_phase method. This phase starts at the same time as the uvm_run_phase unless a user defined phase is inserted in front of this phase.

Upon Entry

• Indicates that power has been applied but not necessarily valid or stable.

• There should not have been any active clock edges before entry into this phase.

Typical Uses

• Wait for power good.

• Components connected to virtual interfaces should initialize their output to X's or Z's.

• Initialize the clock signals to a valid value

• Assign reset signals to X (power-on reset).

• Wait for reset signal to be asserted if not driven by the verification environment.

Exit Criteria

• Reset signal, if driven by the verification environment, is ready to be asserted.

• Reset signal, if not driven by the verification environment, is asserted.

Variables

Name	Type	Description
type_name	string

Functions

static function uvm_pre_reset_phase get ( )

Returns the singleton phase handle

virtual function string get_type_name ( )

Tasks

virtual function exec_task ( uvm_component comp, uvm_phase phase )

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