Class uvm_reg_single_access_seq

• uvm_pkg :: uvm_void

  • uvm_pkg :: uvm_object

    • uvm_pkg :: uvm_transaction

      • uvm_pkg :: uvm_sequence_item

        • uvm_pkg :: uvm_sequence_base

          • uvm_pkg :: uvm_sequence

            • uvm_pkg :: uvm_reg_sequence

              • uvm_pkg :: uvm_reg_single_access_seq

Reset

Inheritance Diagram of uvm_reg_single_access_seq

Verify the accessibility of a register by writing through its default address map then reading it via the backdoor, then reversing the process, making sure that the resulting value matches the mirrored value.

If bit-type resource named "NO_REG_TESTS" or "NO_REG_ACCESS_TEST" in the "REG::" namespace matches the full name of the register, the register is not tested.

uvm_resource_db#(bit)::set({"REG::",regmodel.blk.r0.get_full_name()},
                           "NO_REG_TESTS", 1, this);

Registers without an available backdoor or that contain read-only fields only, or fields with unknown access policies cannot be tested.

The DUT should be idle and not modify any register during this test.

Variables

Name	Type	Description
rg	uvm_reg	The register to be tested

Constructors

function new ( string name )

Tasks

virtual function body ( )

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