[source]

Class uvm_push_sequencer

uvm_pkg::uvm_push_sequencer <REQ, RSP> + req_port : uvm_blocking_put_port #(REQ) + run_phase()

Inheritance Diagram of uvm_push_sequencer

CLASS

uvm_push_sequencer #(REQ,RSP)

Parameters

Name

Default value

Description

REQ

uvm_sequence_item

RSP

REQ

Variables

Name

Type

Description

req_port

uvm_blocking_put_port#(uvm_sequence_item)

The push sequencer requires access to a blocking put interface. A continuous stream of sequence items are sent out this port, based on the list of available sequences loaded into this sequencer.

Typedefs

Name

Actual Type

Description

this_type

uvm_push_sequencer#(REQ, RSP)

Constructors

function new ( string name, uvm_component parent ) [source]

Standard component constructor that creates an instance of this class using the given name and parent , if any.

Tasks

virtual function run_phase ( uvm_phase phase ) [source]

The push sequencer continuously selects from its list of available sequences and sends the next item from the selected sequence out its req_port using req_port.put(item). Typically, the req_port would be connected to the req_export on an instance of a uvm_push_driver #(REQ,RSP), which would be responsible for executing the item.